1. Field of the Invention
The present invention relates to latch and register circuits, and more particularly to a latch circuit which operates with a reduced voltage clock node.
2. Description of the Related Art
Modern microprocessors have multiple operating modes which include multiple power states. The multiple power states include several low power operating states for reducing overall power consumption. Various methods are known for reducing power, such as various combinations of adjusting operating voltage and/or operating frequency among other operating parameters. As an example, the core operating frequency of a microprocessor may be reduced by a significant factor (e.g., 16), and the core voltage may be reduced by half or more of the full power operating voltage. In certain low power states, the voltages of the clocks are reduced. The same reduced clock voltage is applied across the entire chip to maintain phase alignment and avoid phase errors. The same clock voltage is used across the chip die since a higher voltage clock signal would propagate faster across the chip die and arrive at various logic at different times relative to lower voltage clock signals resulting in undesired clock skew disparities.
There are certain conditions or situations in which higher voltage and/or higher frequency signals are used within a microprocessor even during low power operating states. For example, regardless of the power state of the microprocessor, an external bus (e.g., front-side bus) interfacing the microprocessor with external devices may still be operating at full voltage and/or a different frequency. Depending upon the frequency disparity, there may not be sufficient time to level-shift core data signals to the voltage level at the output using conventional level-shift circuits. As another example, the chip die may include a higher voltage portion or “island” operating at increased voltage levels. It is desired to use the same clock across the chip die even during low voltage conditions. There is a need for latching and registering higher voltage data using lower voltage clocks.